Program instructions for a microprocessor are typically stored in sequential, addressable locations within a memory. When these instructions are processed, the instructions may be fetched from consecutive memory locations and stored in a cache commonly referred to as an instruction cache. The instructions may then be retrieved from the instruction cache and executed. Each time an instruction is fetched from memory, a next instruction pointer within the microprocessor may be updated so that it contains the address of the next instruction in the sequence. The next instruction in the sequence may commonly be referred to as the next sequential instruction pointer. Sequential instruction fetching, updating of the next instruction pointer and execution of sequential instructions continues linearly through memory until an instruction, commonly referred to as a branch instruction, is encountered. A branch instruction may refer to an instruction that may result in a change in an address in the next instruction pointer that is not the next sequential address, and thereby causes the flow of the program to be altered. That is, a branch instruction may cause a break in the sequence of instruction execution so that the next instruction executed may not be in sequential order.
Typically, a branch instruction may comprise information in order to calculate what is commonly referred to as the target address, if the branch is taken. The target address is the address of the next instruction to execute. The target address may be calculated after the instruction is fetched from the instruction cache. Typically, a portion of the instruction fetched from the instruction cache comprises an offset of the target address that may be added to the address of the branch instruction to calculate the target address by adders. The number of bits of the offset may differ among various architectures, but the width of the addition is generally the width of the instruction address. In some microprocessor designs, this addition may limit the execution speed of the microprocessor since the addition may utilize valuable processor cycles.
The addition of the offset of the target address in the instruction with the instruction address after the branch instruction is fetched from the instruction cache may be avoided at least in part by encoding the entire target address in the instruction prior to being stored in the instruction cache. That is, the complete target address may be pre-calculated and stored in the branch instruction prior to the branch instruction being stored in the instruction cache. Upon retrieving the branch instruction, the target address may then be simply read from the instruction without any addition. However, by storing the complete target address in the branch instruction, the size of the instruction cache may have to be expanded since the number of bits of the instruction may have to be increased to store the target address. For example, a 32-bit instruction with a 16-bit offset may have to be expanded an additional 16 bits in order to store a 32-bit target address. As a result, the 32-bit instruction may now have to be expanded to 48 bits. Subsequently, each instruction may have to be 48 bits in length instead of 32 bits thereby effectively increasing the instruction cache size by 50%.
It would therefore be desirable to develop a technique for calculating the target address of a branch instruction upon fetching the branch instruction from the instruction cache without implementing adders while not substantially increasing the instruction length.